Title :
A mixed-structure delay locked-loop with wide range and fast locking
Author :
Jo, Youngkwon ; Shim, Yong ; Kim, SooHwan ; Kim, Suki ; Cho, Kwanjun
Author_Institution :
Dept. of Electron. & Comput. Eng., Korea Univ., Seoul
Abstract :
This paper describes an all digital locked-loop (DLL) with a mixed structure of measure-controlled DLL (MCDLL) and register-controlled DLL (RCDLL). The DLL utilized time to digital converter (TDC) and digital to time converter (DTC) using ring counter for wide range operation with small area, fast lock and duty cycle correction (DCC). Simulation results show lock time less than 40 cycles, 1% duty correction error from 50plusmn10% duty external clock, 12mW power dissipation at 800MHz with a 1.5V supply voltage and a wide locking range from 100MHz to 800MHz in a 0.18mum CMOS technology
Keywords :
convertors; delay lock loops; digital phase locked loops; 0.18 micron; 1.5 V; 100 to 800 MHz; 12 mW; CMOS technology; DCC; DTC; MCDLL; RCDLL; TDC; digital locked-loop; digital to time converter; duty correction error; duty cycle correction; duty external clock; measure-controlled DLL; mixed-structure delay locked-loop; power dissipation; register-controlled DLL; ring counter; time to digital converter; CMOS technology; Clocks; Costs; Counting circuits; Delay effects; Delay lines; Digital-to-frequency converters; Frequency; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692990
