Techniques to address increased dimensionality of ASIC library design

We present novel methods that mitigate the impact of high dimensionality of ASIC library during its design and characterization. Specifically, we demonstrate the application of formal optimization during cell size tuning, the use of automated electrical rules checking during design, and the use of novel latch modeling techniques during characterization. We show many-fold improvement in library robustness and sizing effort, and ~2times reduction in latch characterization time