Title :
A cost-effective reconfigurable accelerator for platform-based SOC design
Author :
Van, Lan-Da ; Luo, Hsin-Fu ; Chang, Nien-Hsiang ; Huang, Chun-Ming
Author_Institution :
Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu
Abstract :
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high usage rate and low hardware cost without sacrificing multimedia computation performance. The RCA consisting of 8 type 1 grouped processing elements (GPE1s), 3 GPE2s and 1 GPE3 is capable of configuring two 16times16-bit multiplication, eight 8times8 multiplication, and sixteen 8-bit absolute operations in different connection topologies. Via the cost-effective RCA, the number of GPEs can be saved up to 25% and the usage rates of the RCA compared with that of for motion estimation (ME), RGB2YUV and DCT/IDCT can be improved by 25%, 18.7%, and 23.9%, respectively
Keywords :
digital signal processing chips; discrete cosine transforms; integrated circuit design; motion estimation; reconfigurable architectures; system-on-chip; 16 bit; 8 bit; grouped processing elements; motion estimation; reconfigurable accelerator; reconfigurable computation array; system-on-chip design; Bandwidth; Costs; Design methodology; Digital signal processing; Discrete cosine transforms; Finite impulse response filter; Hardware; High performance computing; System-on-a-chip; Video coding;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693000
