A design language for automatic synthesis of fault trees

The separation of digital system design and reliability analysis incurs unnecessary costs, delays and quality penalties. This paper introduces a graphical design language called RIDL (Reliability Information embedded Design Language) for modeling digital systems. In RIDL, redundancy and failure information is embedded within block diagram schematics, without significantly altering the physical block diagram models typically used by design engineers. A system schematic in RIDL has all of the information needed for reliability analysis without a need for additional textual descriptions. A dynamic fault tree model can be automatically synthesized from a RIDL system model. Designers can use the synthesized fault trees to obtain rough reliability analyses at an early conceptual design stage. To evaluate the potential of this approach, we have applied it to several example systems