Title :
Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability
Author :
Galhardo, A. ; Goes, XJ ; Paulino, N.
Author_Institution :
Campus da Faculdade de Ciencias e Tecnologia, Univ. Nova de Lisboa, Monte da Caparica
Abstract :
This paper proposes a linearization technique for low-distortion high-swing CMOS switches based on a new method of improving the linearity of the NMOS and PMOS conductances. This method has the advantage over conventional clock-boosting techniques of avoiding large gate voltages thus reducing the stress on the gate capacitance. Simulated results of a practical sample-and-hold circuit show that, using this technique, linearity levels compatible with 12-b can be reached over the Nyquist band
Keywords :
CMOS analogue integrated circuits; integrated circuit reliability; linearisation techniques; switching circuits; CMOS switches; NMOS conductances; Nyquist band; PMOS conductances; clock-boosting techniques; gate capacitance; linearization technique; sample-and-hold circuit; stress reduction; CMOS technology; Clocks; Linearity; Linearization techniques; MOS devices; Stress; Strontium; Switches; Switching circuits; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693006
