Scaling limit of silicon nitride gate dielectric for future CMOS technologies

CMOS technology scaling in recent years has reduced the SiO/sub 2/ gate dielectric thickness below 3 nm. Excessive direct tunneling currents through ultra-thin (<2 nm) SiO/sub 2/ necessitates its replacement by dielectrics with higher relative permittivity. Silicon nitride (Si/sub 3/N/sub 4/, k=7.8) (Ma, 1998) is a promising candidate as the first post-SiO/sub 2/ gate dielectric due to its compatibility with conventional CMOS processes. However, there has been relatively little modeling work done on the direct tunneling current through Si/sub 3/N/sub 4/ in comparison to SiO/sub 2/ (Lo et al., 1997; Schuegraf and Hu, 1994). In this paper, we report the characterization and modeling of direct tunneling gate currents through ultra-thin Si/sub 3/N/sub 4/ gate dielectric in CMOS transistors. The model is then used to project the scaling limit of Si/sub 3/N/sub 4/ gate dielectric.