A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications

Author

Shi, Yun ; Rassel, Robert M. ; Phelps, Richard A. ; Candra, Panglijen ; Hershberger, Douglas B. ; Tian, Xiaowei ; Sweeney, Susan L. ; Rascoe, Jay ; Rainey, BethAnn ; Dunn, Jim ; Harame, David

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2010

fDate

23-25 May 2010

Firstpage

237

Lastpage

240

Abstract

In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on R_on and V_off is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics, this JFET device also demonstrates promising RF characteristics such as maximum frequency, linearity, power handling capability, power-added efficiency, indicating a good candidate for RF designs.

Keywords

1/f noise; CMOS integrated circuits; flicker noise; junction gate field effect transistors; JFET optimization; RFCMOS process; flicker noise; junction-FET; size 0.18 micron; 1f noise; CMOS process; CMOS technology; Capacitance; Isolation technology; MMICs; Radio frequency; Silicon; Streaming media; Voltage; 1/f noise; JFET; Ron; RF characteristics; Voff; optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE

Conference_Location

Anaheim, CA

ISSN

1529-2517

Print_ISBN

978-1-4244-6240-7

Type

conf

DOI

10.1109/RFIC.2010.5477348

Filename

5477348