Title :
A novel low-profile low-parasitic RF package using high-density build-up technology
Author :
Wei, Chien-Cheng ; Lin, Ming-Chien ; Fan, Chin-Ta ; Chiang, Ta-Hsiang ; Chiu, Ming-Kuen ; Ru, Shao-Pin ; Ni, Nan ; Cardona, Albert
Author_Institution :
Taipei Hsien, Tong Hsing Electron. Ind., Ltd., Taipei, Taiwan
Abstract :
This paper presents a low-profile low-parasitic RF package by using the high-density build-up (HD-BU) technology. This package achieves much thinner, fine pitch, and exposed design pattern feature for outstanding electrical and thermal performance. The packaging fabrication is simple and only needs several processes. This HD-BU package provides lower parasitic than other lead-frame types due to the use of very thin bonding pads. Additionally, a capacitor chip is assembled using the proposed technology for packaging demonstration and electrical performance evaluation. Based on the experimental results, the measured capacitances at 1-GHz are quite similar before and after packaging. It indicates that the HD-BU package has low parasitic capacitance even at high-frequency operation, and does not affect the electrical performance for the packaged chip. Therefore, these packages are good candidates for applications requiring low profile, low parasitic and low cost.
Keywords :
capacitors; electronics packaging; capacitor chip; design pattern feature; electrical performance evaluation; high density build-up technology; high-density build-up technology; low parasitic capacitance; low profile low parasitic RF package; packaged chip; packaging demonstration; packaging fabrication; Assembly; Bonding; Capacitance measurement; Capacitors; Costs; Fabrication; Packaging; Parasitic capacitance; Radio frequency; Semiconductor device measurement; BST varactor; High-density build-up; RF package; lead-frame;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-6240-7
DOI :
10.1109/RFIC.2010.5477358