Title :
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution
Author :
Seong, Chang-Kyung ; Lee, Seung-Woo ; Choi, Woo-Young
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul
Abstract :
This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 mum CMOS technology. In the measurement, the CDR has plusmn400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 mum times 165mum
Keywords :
CMOS digital integrated circuits; buffer circuits; clocks; reference circuits; 0.18 micron; 1.25 Gbit/s; 1.8 V; 17.8 mW; CDR; CMOS technology; clock and data recovery circuit; delay buffer; digitally-controlled dual-loop circuit; jitter; phase resolution; power consumption; reference clock; CMOS technology; Circuits; Clocks; Delay; Energy consumption; Jitter; Phase locked loops; Prototypes; Switches; Working environment noise;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693034
