Control flow graph reconstruction for assembly language programs with delayed instructions

Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to a higher level language, we need to construct a control flow graph (CFG). However CFG construction is complicated by architectural features which include VLIW parallelism, predicated instructions and branches with delay slots. We describe an efficient algorithm for the construction of a CFG, where the parallelism has been eliminated, instructions are reordered and delay slots have been eliminated. The algorithm´s effectiveness has been demonstrated by its use in a reverse compiler for the Texas Instruments C60 series of digital signal processors.