• DocumentCode
    2539197
  • Title

    Multiple-valued memory operation in SiN-based single-electron memory

  • Author

    Sunamura, H. ; Kawaura, H. ; Sakamoto, T. ; Baba, T.

  • Author_Institution
    NEC Fundamental Res. Labs., Tsukuba, Japan
  • fYear
    2000
  • fDate
    19-21 June 2000
  • Firstpage
    153
  • Lastpage
    154
  • Abstract
    Multiple-valued memory operation is one of the keys for future high-density memory devices since it significantly increases memory capacity per unit area. We previously reported a single electron memory device that utilizes traps in a silicon nitride (SiN) layer as the memory node and an ultra-sensitive Al/AlO/sub x/ single-electron transistor (SET) for readout (Sunarmura et al., 1999). In this work, we propose a new device structure in which a new layered structure is designed so that only electrons can participate in the device characteristics. With this new device structure, we successfully achieve multiple-valued single-electron memory operation of up to nine values for the first time. An oscillating behavior in SET output current (I/sub SET/) during write/read processes due to electron trapping/detrapping at the traps is used to represent multiple values.
  • Keywords
    digital readout; electric current; electron traps; multivalued logic; nanotechnology; semiconductor storage; silicon compounds; single electron transistors; Al-AlO; SET output current; SiN; SiN layer traps; SiN-based single-electron memory; device characteristics; device structure; electron detrapping; electron trapping; layered structure design; memory capacity; memory device density; memory node; multiple value representation; multiple-valued memory operation; multiple-valued single-electron memory operation; oscillating behavior; single electron memory device; ultra-sensitive Al/AlO/sub x/ SET readout; ultra-sensitive Al/AlO/sub x/ single-electron transistor readout; write/read processes; Electron traps; Insulation; Laboratories; National electric code; Oxidation; Silicon compounds; Single electron memory; Single electron transistors; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference, 2000. Conference Digest. 58th DRC
  • Conference_Location
    Denver, CO, USA
  • Print_ISBN
    0-7803-6472-4
  • Type

    conf

  • DOI
    10.1109/DRC.2000.877128
  • Filename
    877128