DocumentCode :
2539212
Title :
GaAs single electron transistors and logic inverters based on Schottky wrap gate structures
Author :
Kasai, S. ; Hasegawa, H.
Author_Institution :
Res. Center for Interface Quantum Electron., Hokkaido Univ., Sapporo, Japan
fYear :
2000
fDate :
19-21 June 2000
Firstpage :
155
Lastpage :
156
Abstract :
Summary form only given. Due to the availability of precisely controllable heteroepitaxy and superb electron transport, III-V compound semiconductor single electron integrated circuits are promising candidates for next generation electronics featuring ultra-small delay-power products near the quantum limit and ultra-high circuit densities. The key issue is to establish single electron transistor (SET) structures that can realize sufficient circuit performance and high-density integration. This paper presents novel GaAs SETs and SET logic inverters utilizing the Schottky wrap gate (WPG) structure (Kasai et al, Jpn. J. Appl. Phys. vol. 36, p. 1678, 1997). The advantages of WPG devices are stronger electron confinement than the traditional split gate structure, device design flexibility, and fabrication process simplicity. In the basic WPG structure, a nanometer-length Schottky gate is wrapped around an etched AlGaAs-GaAs trapezoidal nanowire to strongly confine electrons. In the 2-gate WPG SET structure, complete depletion underneath the WPGs forms double tunnel barriers with a quantum dot (QD) in between. A tighter dot potential control is expected in the 3-gate WPG SET.
Keywords :
III-V semiconductors; Schottky barriers; etching; gallium arsenide; integrated logic circuits; logic gates; nanotechnology; semiconductor quantum dots; semiconductor quantum wires; single electron transistors; AlGaAs-GaAs; GaAs; GaAs SET logic inverters; GaAs SETs; GaAs single electron transistor logic inverters; GaAs single electron transistors; III-V compound semiconductor single electron integrated circuits; SET structures; Schottky WPG structure; Schottky wrap gate structures; WPG devices; WPG structure; circuit density; circuit performance; controllable heteroepitaxy; delay-power products; device design flexibility; double tunnel barriers; electron confinement; electron transport; etched AlGaAs-GaAs trapezoidal nanowire; fabrication process simplicity; high-density integration; nanoscale Schottky gate; quantum dot; quantum dot potential control; quantum limit; single electron transistor structures; split gate structure; sub-WPG depletion; three-gate WPG SET; two-gate WPG SET structure; Circuit optimization; Delay; Electron traps; Etching; Fabrication; Gallium arsenide; III-V semiconductor materials; Nanostructures; Pulse inverters; Single electron transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Device Research Conference, 2000. Conference Digest. 58th DRC
Conference_Location :
Denver, CO, USA
Print_ISBN :
0-7803-6472-4
Type :
conf
DOI :
10.1109/DRC.2000.877129
Filename :
877129
Link To Document :
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