A 40-Gbit/s-class universal logic interfacer IP using GaAs HBTs for heterogeneous logic/device systems in package

Author

Otsuji, Taiichi ; Takahashi, Seigo ; Hamasuna, Noburo ; Takada, Toshiaki ; Matsuoka, Yutaka

Author_Institution

Dept. of Syst. Innovation & Informatics, Kyushu Inst. of Technol., Fukuoka, Japan

fYear

2004

fDate

24-27 Oct. 2004

Firstpage

251

Lastpage

254

Abstract

A 40-Gbit/s-class ECL/SCFL-to-LVCMOS/LVDS universal logic interfacer IP was developed using production-level GaAs HBTs for use in a heterogeneous logic/device system in package (SiP). A unique co-design concept based on the flat and modular IP configurations was introduced to make ease of seamless/universal interconnection with reduced design/test costs. The test chip demonstrated excellent universal level-transform functions with a small power-delay product of less than 2.8 pJ.

Keywords

CMOS logic circuits; III-V semiconductors; emitter-coupled logic; field effect logic circuits; gallium arsenide; integrated circuit design; system-on-chip; 40 Gbits/s; GaAs; GaAs HBT; IP configurations; LVCMOS; LVDS; emitter coupled logic; heterogeneous logic device systems in package; power-delay product; source coupled FET logic; universal interconnection; universal level-transform functions; universal logic interfacer IP; Costs; Gallium arsenide; Heterojunction bipolar transistors; Informatics; Integrated circuit interconnections; Logic circuits; Logic design; Logic devices; Packaging; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2004. IEEE

ISSN

1550-8781

Print_ISBN

0-7803-8616-7

Type

conf

DOI

10.1109/CSICS.2004.1392553

Filename

1392553