Title :
2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR
Author :
Mazouffre, O. ; Toupé, R. ; Pignol, M. ; Deval, Y. ; Begueret, J.B.
Author_Institution :
IMS Lab., Univ. of Bordeaux, Talence, France
Abstract :
A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; clocks; injection locked oscillators; satellite links; CMOS bulk process; CMOS fully integrated ILO-based CDR; I/O buffers; STMicroelectronics; analog phase alignment circuit; bit error rate; bit rate 2 Gbit/s to 4.3 Gbit/s; bit rate 9 Gbit/s to 12.1 Gbit/s; clock recovery function; injection locked oscillator; overall power dissipation; power 220 mW; power 400 mW; power 480 mW; satellite data link; size 130 nm; voltage 300 V; voltage 440 V; Bandwidth; Circuits; Clocks; Detectors; Injection-locked oscillators; Jitter; Phase detection; Phase locked loops; Satellites; Voltage-controlled oscillators; CDR; CMOS; Clock and data recovery circuit; ILO; Injection Locked Oscillator; Satellite; gigabit;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-6240-7
DOI :
10.1109/RFIC.2010.5477391
