A thirty two element phased-array transceiver at 60GHz with RF-IF conversion block in 90nm flip chip CMOS process

A 60 GHz 32 element bidirectional phased-array TX/RX chip with a 2 bit phase shifter and IF converter to/from 12GHz, using 90nm CMOS process, is described. The array features 12.5 dB gain, noise figure (NF) of 11 dB, IP1dB of -17dbm for RX, and total output Psat of +8dBm for TX, drawing 390 mA from a 1.3-V supply. The RMS amplitude and phase error of the phase shifter is 0.8dB and 5° max respectively from 57 to 66 GHz. The paper emphasizes the flip-chip assembly technology selected and its impact on performance, and the phase and amplitude errors resulted by physical impairments such as the finite isolation between different chains. Special test structures were designed to measure bump isolation and insertion loss (IL). The designed architecture together with the compact layout results in a die area of 14.5mm² for the full array. To our knowledge, this is the first report on a large bidirectional 60 GHz array, with the lowest reported chip power consumption and size.