Title :
WL-VC SRAM: a low leakage memory circuit for deep sub-micron design
Author :
Razavipour, Ghasem ; Motamedi, Ahmad ; Afzali-Kusha, Ali
Author_Institution :
Dept. of Electr. Eng., Amirkabir Univ. of Technol., Tehran
Abstract :
In this paper, a static random access memory (SRAM) cell that reduces the gate leakage power with low access latency is proposed. The technique reduces the gate leakage current both in the zero and in the one states. The efficiency of the design is evaluated by simulating the circuit in a 45-nm CMOS technology. Compared to the conventional SRAM cell, the proposed design reduces the total gate leakage current around 58% for an oxide thickness of 1.4nm. The increase in the area of the proposed cell is minimal compared to the conventional SRAM. The read access time of this SRAM is only 5.6% slower than that of the conventional SRAM
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; logic design; 1.4 nm; 45 nm; CMOS technology; WL-VC SRAM; deep submicron design; gate leakage current; gate leakage power; low access latency; low leakage memory circuit; oxide thickness; static random access memory; CMOS technology; Circuits; Gate leakage; Leakage current; MOSFETs; Power dissipation; Power engineering computing; Random access memory; Tunneling; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693065
