A 2-GHz CMOS variable gain amplifier optimized for low noise

Author

Charles, Cameron T. ; Allstot, David J.

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA

fYear

2006

fDate

21-24 May 2006

Abstract

An analysis of the noise performances of the current steering and simple cascode variable gain amplifier topologies is presented. Simulation results are used to determine the dominant noise sources at reduced gain levels, and analytical techniques are used to obtain a sizing strategy for minimizing the overall noise figure. The optimum configuration is shown to be a current steering topology with unequal sizing for the current steering transistors. Using simulations for the final sizing optimization, a current steering variable gain amplifier has been designed in 0.18 mum CMOS technology. The amplifier consumes 8 mW of power, has a maximum S21 of 20.6 dB, a noise figure of 1.47 dB at the maximum gain, and a noise figure of 8.8 dB when the gain is reduced by 20 dB

Keywords

CMOS analogue integrated circuits; S-parameters; UHF amplifiers; UHF integrated circuits; integrated circuit noise; low noise amplifiers; 0.18 micron; 1.47 dB; 2 GHz; 20 dB; 20.6 dB; 8 mW; 8.8 dB; CMOS variable gain amplifier; current steering transistors; noise figure; sizing optimization; Analytical models; CMOS technology; Design optimization; Low-noise amplifiers; Noise figure; Noise level; Noise reduction; Performance analysis; Performance gain; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693082

Filename

1693082