FPGA Based Parallel Thinning for Binary Fingerprint Image

Author

Xu, Hui ; Qu, Yifan ; Zhang, Yan ; Zhao, Feng

Author_Institution

Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2009

fDate

4-6 Nov. 2009

Firstpage

1

Lastpage

4

Abstract

A critical step in fingerprint recognition is to skeletonize the fingerprint image for minutiae extraction, which is recognized as "thinning" in image processing. The speed and reliability of the thinning process are important for the whole fingerprint identification system. In this paper, to accelerate the thinning process, a fast hardware thinning algorithm is implemented on the Xilinx Virtex II Pro developing system with a highly-paralleled architecture. Appealing experimental result is presented and the advantage of hardware thinning is also explored.

Keywords

field programmable gate arrays; fingerprint identification; image thinning; parallel architectures; FPGA-based parallel thinning; Xilinx Virtex II Pro; binary fingerprint image; fingerprint identification system; fingerprint image skeletonization; fingerprint recognition; hardware thinning algorithm; image processing; minutiae extraction; parallel architecture; Acceleration; Biometrics; Computer architecture; Field programmable gate arrays; Fingerprint recognition; Frequency estimation; Hardware; Image matching; Image recognition; Software algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Pattern Recognition, 2009. CCPR 2009. Chinese Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-4199-0

Type

conf

DOI

10.1109/CCPR.2009.5343964

Filename

5343964