Title :
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier
Author :
He, Yajuan ; Chang, Chip-Hong
Author_Institution :
Centre for Integrated Circuits & Syst., Nanyang Technol. Univ.
Abstract :
In this paper, a power-delay efficient redundant binary (RB) to 2´s complement number converter for RB multiplication is presented. A new conversion algorithm is proposed to fully exploit the redundancy of RB encoding for a VLSI efficient implementation. The hierarchical linear expansion of the carry equation creates a regular multi-level parallel structure which is well suited for implementation with a logarithmic depth hybrid carry-lookahead/carry-select (CLA/ CSL) adder. A special add-one circuit is also incorporated into the CSL circuit to further reduce its logic complexity. A 64-bit reverse converter is designed using TSMC 0.18 mum CMOS Technology. Pre-layout HSPICE simulation of the proposed design shows that it is capable of completing a 64-bit conversion in 761 ps and dissipates merely 0.34 mW at a data rate of 100MHz and a supply voltage of 1.8V
Keywords :
CMOS integrated circuits; adders; carry logic; convertors; multiplying circuits; redundancy; redundant number systems; 0.18 micron; 0.34 mW; 1.8 V; 100 MHz; 64 bit; CMOS technology; CSL circuit; HSPICE simulation; RB encoding; RB-to-NB converter; VLSI; add-one circuit; binary multiplier; carry equation; carry-lookahead adder; carry-select adder; hierarchical linear expansion; logic complexity; multilevel parallel structure; redundancy; reverse converter; Adders; CMOS logic circuits; CMOS technology; Circuit simulation; Encoding; Helium; Integrated circuit technology; Logic circuits; Logic design; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693107
