Modified CAEN-BIST algorithm for better utilization of nanofabrics

In the last 40 years there has been an exponential increase in the number of transistors per processor. This increase has been according to Moorepsilas law that predicted the number of transistors that could be placed on the chip would double every two years. However, there are some challenges like leakage currents, process variation, costs and reliability issues like NBTI and HCI that may result to the end of scaling. A solution to CMOS scaling problems is based on architectures that use nanoelectronic devices. The main problem with these devices is their high defect rates due to their bottom up assembly. The reconfigurability of these architectures enables them to manage the high amount of defects. So, to use these architectures the defects should be found and after that in the mapping phase the defective elements are configured around. One of the architectures based on nanoelectronic devices is the nanofabric architecture proposed by Goldstein and Budiu [3]. Different algorithms have been proposed for finding defect map of nanofabric. One of them is proposed by Brown and Blanton [2]. In this paper a modification in CAEN-BIST algorithm has been proposed which improves the nanoblock defect density, test time and utilization of nanoblocks.