A compact 190 /spl mu/W PLL for clock control and distribution in ultra-large scale ICs

Author

Allan, Gord ; Knight, John

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont.

fYear

2006

fDate

21-24 May 2006

Lastpage

2464

Abstract

A compact low-power PLL is implemented in 0.18 mum CMOS for clock management and distribution. Like digital PLLs, it is composed of standard-cells, can be mixed with regular logic, and is digitally placed & routed, but it does not suffer from quantization jitter. At most 0.008 mm² (650 `gates´), as times32 clock multiplier it consumes only 190 mu;W @ 128 MHz. It can perform efficient clock distribution, cleansing a noisy low-frequency reference and synchronizing outputs with jitter below 46ps_{pk - pk}. With lock-range between 60-172 MHz, adjustable loop dynamics and partial state-memory it is less than 1/5th the size and 1/15th the power of PLLs at similar frequencies

Keywords

CMOS integrated circuits; ULSI; clocks; jitter; low-power electronics; phase locked loops; 0.18 micron; 190 mW; 60 to 172 MHz; CMOS integrated circuit; adjustable loop dynamics; clock control; clock distribution; clock management; clock multiplier; compact phase locked loop; partial state-memory; ultra-large scale integrated circuit; Clocks; Costs; Digital integrated circuits; Filtering; Flip-flops; Fluctuations; Jitter; Phase frequency detector; Phase locked loops; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693121

Filename

1693121