Linearity test for high resolution DACs using low-accuracy DDEM flash ADCs

Author

Xing, Hanqing ; Chen, Degang ; Geiger, Randall

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA

fYear

2006

fDate

21-24 May 2006

Lastpage

2472

Abstract

This work proposed a built-in self-test (BIST) strategy for DAC linearity test by utilizing the deterministic dynamic element matching (DDEM) technique in a common flash ADC. DDEM technique allows low-resolution and low-accuracy ADCs work as test devices. In order to provide high resolution/accuracy test abilities, a fine quantization stage and an input dithering DAC are incorporated. In this paper, the architecture of the test system and the test procedure are described. The test performance is analyzed theoretically and verified by numerical simulation. Simulation results show that a two-step flash ADC composed of a 6-bit coarse DDEM stage and a 6-bit fine stage, plus an incorporated 5-bit dithering DAC, with linearity of all the blocks no more than 6 bits, is capable of testing 14-bit DACs

Keywords

built-in self test; digital-analogue conversion; numerical analysis; quantisation (signal); 14 bit; 5 bit; 6 bit; BIST; analog digital conversion; built-in self-test; deterministic dynamic element matching; digital-analog conversion; fine quantization stage; flash ADC; high resolution DAC; linearity test; low-accuracy DDEM; Algorithm design and analysis; Automatic testing; Built-in self-test; Linearity; Numerical simulation; Performance analysis; Quantization; Signal design; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693123

Filename

1693123