A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Author

Ping, Lu ; Fan, Ye ; Junyan, Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

fYear

2006

fDate

21-24 May 2006

Abstract

A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter´s requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes

Keywords

CMOS integrated circuits; frequency synthesizers; interpolation; local area networks; oscillators; transceivers; 0.18 micron; 1.8 V; 10/100Base-T mode; 1000Base-T mode; CMOS technology; crystal oscillator; degressive interpolating resistors; dynamic phase interpolation; dynamic voltage-mode phase interpolator; high-speed Ethernet transceiver; low-jitter frequency synthesizer; time-interval clocks; CMOS technology; Clocks; Ethernet networks; Frequency synthesizers; Interpolation; Jitter; Resistors; Transceivers; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693126

Filename

1693126