A DTCNN circuit proposal for pixel-level snakes

Author

Brea, V.M. ; Vilarino, D.L. ; Cabello, D.

Author_Institution

Dept. de Electron. e Comput., Santiago de Compostela Univ., Spain

fYear

2000

fDate

2000

Firstpage

425

Lastpage

430

Abstract

A VHDL description of a DTCNN circuit for pixel-level snakes is given. This is the first of successive steps in a top-down design flow towards a final physical implementation. The complexity of the application leads us to make use of a multilayer DTCNN with cyclic time variable cloning templates. In order to make a feasible physical implementation, the basic concepts of the CNN Universal Machine (CNNUM) have been adopted: distributed memory and programming templates. In addition, some other approaches like the use of 2Q multipliers are followed. The validity of the proposed structure is illustrated by simulations of a 9×9 network

Keywords

cellular neural nets; hardware description languages; image segmentation; neural chips; 2Q multipliers; 9×9 network; CNN Universal Machine; DTCNN circuit; cyclic time variable cloning templates; pixel-level snakes; programming templates; top-down design flow; Active contours; Cellular neural networks; Circuits; Force control; Image segmentation; Nonhomogeneous media; Parallel processing; Pixel; Proposals; Turing machines;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications, 2000. (CNNA 2000). Proceedings of the 2000 6th IEEE International Workshop on

Conference_Location

Catania

Print_ISBN

0-7803-6344-2

Type

conf

DOI

10.1109/CNNA.2000.877366

Filename

877366