Design and implementation of semi-quadratic slope compensation circuit for PWM peak current mode boost regulator

This paper presents a circuit implementation to fulfill the demand of the non-linear slope compensation to improve stability in a switching peak current mode DC-DC boost converter. The circuit is implemented by regular threshold voltage NMOS and PMOS and standard on-chip pico-Farad range capacitor biased by a PTAT current. Using the quadratic nature of the drain current of a MOS device in saturation the circuit generates a compensating slope signal on a cycle by cycle basis and this compensating slope signal is added with the current sense signal to compensate the disturbance that might arise. Along with the quadratic nature current another fixed current is added to compensate the noise that creates instability at lower duty cycle where the sense signal is weak. A chip is fabricated in 0.5 mum technology using the proposed circuit. Simulation and test data has been presented.