• DocumentCode
    2542209
  • Title

    An application specific integrated circuit for optimization of fixed polarity reed-muller expressions

  • Author

    Kamal, Tahseen ; Khan, Mozammmel H A

  • Author_Institution
    Dept. of Electr. & Electron. Eng., East West Univ., Dhaka
  • fYear
    2008
  • fDate
    20-22 Dec. 2008
  • Firstpage
    721
  • Lastpage
    726
  • Abstract
    EXOR-based logic circuits have become more popular than AND-OR circuits because they have some specific advantages over AND-OR realizations. Two-level AND-EXOR logic is one of the EXOR-based logics, which is also known as Reed-Muller logic. A Fixed Polarity Reed-Muller (FPRM) expression is one of the seven classes of AND-EXOR logic expressions. An FPRM expression is canonical and uses a fixed polarity for each variable. An n-variable function has 2n different polarity vectors; consequently, there are 2n different FPRM expressions. The expression with minimum number of products is the minimum FPRM expression. Therefore, the minimization problem of FPRM expressions is to find a polarity vector that produces an FPRM expression with minimum number of products. There are many software methods for FPRM minimization which are sequential in nature and require exponential execution time. In this work an ASIC has been developed to minimize 3-variable FPRM expressions which is parallel in nature and requires constant time. This ASIC takes the minterm coefficients of a Boolean function as input. It generates all the polarity vectors for a three variable function and determines the optimum polarity and corresponding FPRM coefficients.
  • Keywords
    Boolean functions; Reed-Muller codes; application specific integrated circuits; field programmable gate arrays; integrated logic circuits; ASIC; Boolean function; EXOR-based logic circuits; FPGA; application specific integrated circuit; fixed polarity Reed-Muller expression; n-variable function; polarity vectors; Application software; Application specific integrated circuits; Boolean functions; Computer science; DH-HEMTs; Eyes; Logic circuits; Logic functions; Minimization methods; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on
  • Conference_Location
    Dhaka
  • Print_ISBN
    978-1-4244-2014-8
  • Electronic_ISBN
    978-1-4244-2015-5
  • Type

    conf

  • DOI
    10.1109/ICECE.2008.4769303
  • Filename
    4769303