Novel C-testable design for H.264 Integer Motion Estimation

H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for testing H.264-IME block, but the test time usually increases as the design grows. In this paper, a C-testable DFT (Design-for-Testability) scheme at bit-plane level is proposed by using the Iterative-Logic-Array (ILA) architecture for the largest part in H.264-IME block. A simple BIST (built-in self-test) circuit is also proposed due to the ILA architecture, and the number of test pattern (NTP), hardware overhead (HO) and delay-time overhead (DTO) are only about 192, 4.70% and 5.56% respectively. The proposed DFT scheme reduces the test time and test cost significantly.