Improved VLSI circuit performance using localized power decoupling

Power droop in the silicon is a major cause for system performance degradation. Higher frequency of operation and reduced power levels are limiting the timing and voltage budget, which is designed in circuits to account for system noise, which includes voltage drooping due to inductive losses. Novel techniques are evolving to compensate for these losses at all levels, starting from motherboard, package, down in to silicon. Due to lack of available space and design constraints, decoupling at the die level is very limited. In this paper a proposal is made to provide for decoupling at the CMOS levels, right where the power is needed. Advanced technology for DRAM capacitors is proposed for use in this paper for the decoupling strategy. Simulation of sub 100 nm multi-metal layer circuit demonstrates the advantage of proposed localized decoupling.