Approximation of critical area of ICs with simple parameters extracted from the layout

In order to have an efficient yield model to compare and predict yields of different products for a fixed manufacturing process, it is necessary to measure a lot of parameters such as critical area of each mask level, yields of elementary process steps, etc. Obtaining values of all the required parameters in an industrial context is often very difficult, and the resulting yield model becomes almost useless, and at least very cumbersome to exploit. Simpler models have been proposed that often tradeoff simplicity for precision of the results. Most of these assume that the chip critical area is proportional to the die area. Other have used the number of transistors as a yardstick to compare chip yields for ASICs generated with a common design system. This paper proposes a new set of parameters derived from the layout of each chip that may be used to assess the yield of a new IC based on a known manufacturing process. This proposal is based on the results of several efficient statistical techniques that are described and applied to a database of approximately one million chips