A high-speed, low-power interleaved trace-back memory for Viterbi decoder

Author

Israsena, Pasin ; Kale, Izzet

Author_Institution

Thailand IC Design Incubator, National Electron. & Comput. Technol. Center, Pathumtani

fYear

2006

fDate

21-24 May 2006

Lastpage

2804

Abstract

This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The trace-back memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 mum CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps

Keywords

CMOS memory circuits; Viterbi decoding; interleaved storage; low-power electronics; 0.35 micron; 1.1 Gbit/s; 232 pJ; AMS CMOS; SoftIP approach; Viterbi decoder; clock signal; high-speed characteristic; low-power consumption; power-aware control signals; registers array; trace-back memory; Clocks; Digital signal processing; GSM; High speed integrated circuits; Maximum likelihood decoding; Phasor measurement units; Random access memory; Read-write memory; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693206

Filename

1693206