DocumentCode
2542676
Title
An implementation of AES algorithm Based on FPGA
Author
Wang Wei ; Chen Jie ; Xu Fei
Author_Institution
Sch. of Electron. Eng. & Autom., Tianjin Polytech. Univ., Tianjin, China
fYear
2012
fDate
29-31 May 2012
Firstpage
1615
Lastpage
1617
Abstract
An implementation of high speed AES algorithm based on FPGA is presented in this paper in order to improve the safety of data in transmission. The mathematic principle, encryption process and logic structure of AES algorithm are introduced. So as to reach the porpose of improving the system computing speed, the pipelining and papallel processing methods were used. The simulation results show that the high-speed AES encryption algorithm implemented correctly. Using the method of AES encryption the data could be protected effectively.
Keywords
cryptography; field programmable gate arrays; mathematical analysis; multiprocessing systems; parallel processing; AES algorithm; FPGA; encryption process; logic structure; mathematic principle; parallel processing methods; pipelining processing methods; Algorithm design and analysis; Clocks; Educational institutions; Encryption; Field programmable gate arrays; Galois fields; AES; Encryption System; FPGA;
fLanguage
English
Publisher
ieee
Conference_Titel
Fuzzy Systems and Knowledge Discovery (FSKD), 2012 9th International Conference on
Conference_Location
Sichuan
Print_ISBN
978-1-4673-0025-4
Type
conf
DOI
10.1109/FSKD.2012.6233811
Filename
6233811
Link To Document