A high-speed low-energy dynamic PLA using an input-isolation scheme

Author

Molavi, Reza ; Mirabbasi, Shahriar ; Saleh, Resve

Author_Institution

Dept. of Electr. & Comput. Eng., British Columbia Univ.

fYear

2006

fDate

21-24 May 2006

Lastpage

2888

Abstract

Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic arrays must be able to compete with standard ASIC designs. This paper proposes a CMOS PLA based on a dynamic NOR architecture that uses an input-isolation technique along with a latch-based sense amplifier to achieve both high operating speed and low-energy consumption. The proposed architecture is designed and simulated in a 0.18mum CMOS technology. It improves the delay by 10% compared with the fastest reported PLA. It also achieves the lowest power-delay product of all other reported dynamic PLAs

Keywords

CMOS logic circuits; NOR circuits; flip-flops; low-power electronics; programmable logic arrays; 0.18 micron; PLA; dynamic NOR architecture; input-isolation; latch-based sense amplifier; structured logic arrays; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Delay; Energy consumption; Isolation technology; Logic arrays; Logic design; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693227

Filename

1693227