A new high speed dynamic PLA

This paper presents a new high speed dynamic programmable logic array (DPLA). The conventional level-restored mechanism is eliminated by using a straightforward CMOS inverter at the charge sharing node on the discharge path. This inverter acts as a voltage monitor and can reduce the voltage swing to 1/2 V_dd at the product lines or output lines. Thus power saving as well as high speed operation can be achieved. In addition, the smallest size inverter can be easily integrated to the design automation of DPLA without augmenting the structure of PLA. Furthermore, this design simplifies the design effort of buffering NAND gates and almost removes the serious glitch problem. Experimental results show that our proposed DPLA can be operated at high speed (>1GHz) with very small power delay product (PDP)