Implementation aspects of the DPA-resistant logic style MDPL

An important task when implementing cryptographic algorithms in hardware is to provide adequate protection against differential power analysis (DPA) attacks. During the last years, several countermeasures against these attacks have been proposed. One of them is a logic style called masked dual-rail pre-charged logic (MDPL). This article discusses several implementation aspects of this logic style. First, it is shown how MDPL circuits can be built using a semi-custom design flow. Subsequently, the area requirements, the speed, the power consumption and the DPA resistance of MDPL circuits are analyzed based on a case study. This case study shows that the power consumption of MDPL circuits is significantly higher than the one of corresponding CMOS circuits. Motivated by this observation, new low-power techniques for MDPL circuits are proposed. During the time when MDPL circuits do not perform operations that are critical for DPA attacks, the proposed low-power techniques reduce the power consumption of MDPL circuits by about a factor of four