DocumentCode
2543235
Title
Through-Silicon-Via technology for stacked thin Si device wafers
Author
Ohba, Takayuki
Author_Institution
Grad. Sch. of Eng., Univ. of Tokyo, Tokyo, Japan
fYear
2011
fDate
9-10 June 2011
Firstpage
61
Lastpage
66
Abstract
This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless TSV processes, as well as the characteristics of SRAM and FRAM devices after thinning the wafers to less than 10 μm.
Keywords
SRAM chips; elemental semiconductors; silicon; three-dimensional integrated circuits; 3D integration; FRAM devices; SRAM devices; Si; bumpless TSV process; stacked thin device wafers; through-silicon-via technology; Copper; Junctions; Manufacturing; Silicon; Stacking; Three dimensional displays; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology (IWJT), 2011 11th International Workshop on
Conference_Location
Kyoto
Print_ISBN
978-1-61284-131-1
Type
conf
DOI
10.1109/IWJT.2011.5970000
Filename
5970000
Link To Document