Title :
Through-Silicon-Via technology for stacked thin Si device wafers
Author_Institution :
Grad. Sch. of Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless TSV processes, as well as the characteristics of SRAM and FRAM devices after thinning the wafers to less than 10 μm.
Keywords :
SRAM chips; elemental semiconductors; silicon; three-dimensional integrated circuits; 3D integration; FRAM devices; SRAM devices; Si; bumpless TSV process; stacked thin device wafers; through-silicon-via technology; Copper; Junctions; Manufacturing; Silicon; Stacking; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Junction Technology (IWJT), 2011 11th International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
978-1-61284-131-1
DOI :
10.1109/IWJT.2011.5970000
