Second order dynamic element matching technique for low oversampling delta sigma ADC

Author

Gupta, Amit Kumar ; Sanchez-Sinencio, Edgar ; Karthikeyan, S. ; Koe, Wern Ming ; Park, Yong-In

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX

fYear

2006

fDate

21-24 May 2006

Lastpage

2976

Abstract

There has been an increased interest in design of broadband (data rate >1MSPS) delta sigma ADCs with over-sampling ratios (OSR) as low as four. Most of these designs are switched capacitor based and use internal multi-bit DACs. With the widely used first order dynamic element matching, the SNDR of these converters is limited by the inherent capacitor matching. We propose a modified second order dynamic element matching technique to alleviate this problem for broadband ADCs, which target a SNDR greater than 100dB

Keywords

analogue-digital conversion; delta-sigma modulation; switched capacitor networks; OSR; SNDR; capacitor matching; delta sigma ADC; first order dynamic element matching; internal multi-bit DAC; over-sampling ratios; second order dynamic element matching technique; switched capacitor based design; Calibration; Capacitors; Clocks; Instruments; Linearity; Multi-stage noise shaping; Noise shaping; Quantization; Signal to noise ratio; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693249

Filename

1693249