A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz

Author

Aghdam, Esmaeil Najafi ; Benabes, Philippe

Author_Institution

Dept. of Signal Process. & Electron. Syst., SUPELEC, Gif sur Yvette

fYear

2006

fDate

21-24 May 2006

Abstract

A robust and hardware efficient dynamic element matching (DEM) algorithm is developed and used to design a 4^th-order bandpass (BP) mismatch-shaping circuit, moved inside the feedback loop of a 6^th-order bandpass continuous-time delta-sigma modulator. This algorithm is based on a shortened tree-structured scheme (STDEM) which can assure a stable high order mismatch-shaping with a modest circuit volume. The modulator has a 3-bit quantizer and 8 thermometric feedback DAC´s cells. The designed DEM´s circuits is simulated in 0.35mum-CMOS which can be clocked up to 300-MHz. The mismatch error floor is decreased of about 35dB in the band of interest. Its related circuit occupies of about 0.22mm² area

Keywords

CMOS integrated circuits; band-pass filters; continuous time filters; delta-sigma modulation; trees (mathematics); 0.35 micron; 3 bit; 300 MHz; DEM circuits; delta-sigma modulator; dynamic element matching algorithm; fourth-order bandpass mismatch-shaping circuit; high order mismatch-shaping; mismatch error floor; second-order dynamic element matching circuit; shortened tree-structured scheme; sixth-order bandpass continuous-time modulator; Algorithm design and analysis; Clocks; Delta modulation; Feedback circuits; Feedback loop; Frequency; Hardware; Noise reduction; Robustness; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693250

Filename

1693250