Digital scheme for quantizer and integrator swing reduction in multibit sigma-delta modulator

This paper proposes a scheme for reducing the maximum swing requirement of the integrator and quantizer in a delta-sigma modulator and discusses its advantages. This technique makes the modulator less sensitive to amplifier non-linearities in the integrator. Moreover, the number of comparators in the multibit quantizer can be greatly reduced since the quantizer only needs to resolve signals with maximum amplitude much less than its own full-scale. Therefore, power and area for the quantizer and loading on the integrator that precedes the quantizer are also reduced. The additional circuitry needed in this scheme can be easily implemented in digital domain