DocumentCode :
2543768
Title :
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique
Author :
Weng, Jun-Hong ; Tsai, Meng-Ting ; Lin, Jung-Mao ; Yang, Ching-Yuan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung
fYear :
2006
fDate :
21-24 May 2006
Lastpage :
3076
Abstract :
In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-mum CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data
Keywords :
CMOS integrated circuits; clocks; optical communication; oscillators; phase detectors; synchronisation; 0.18 micron; 1.8 Gbit/s; CMOS technology; burst-mode clock recovery circuit; data recovery circuit; optical communication system; phase control; phase detector; CMOS technology; Circuits; Clocks; Delay; Optical fiber communication; Phase detection; Phase frequency detector; Phase locked loops; Signal generators; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1693274
Filename :
1693274
Link To Document :
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