Ladder derived switched-current decimators

A bilinear-transformed, elliptic switched-current decimator based on a combination of polyphase networks and a low sensitivity ladder structure has been demonstrated with an M=2 fold reduction in sampling rate. Settling time for the memory cells is maximised by the use of polyphase FIR networks and operating the prototype filter within the decimator at the lower sampling rate. The proposed FIR-IIR cascade (FIC) decimator requires a few extra unit delays, but is simpler to derive, and possesses sensitivity characteristics superior to the reference filter, the recently proposed MFI-type and direct-form II decimator