Title :
Reconfigurable architectures for mesh-arrays with PE and link faults
Author :
Takanami, Itsuo ; Horita, Tadayoshi
Author_Institution :
Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
Abstract :
We propose reconstruction architectures for mesh-arrays with link faults as well as processor element (PE) faults. First, we explain a method for compensating link faults and give a compensation algorithm for the case where no PE is faulty. Then, the reliabilities of the proposed interconnection networks are obtained by computer simulation and are compared with that of the network with doubly duplicated links. Next, we show how PE faults are compensated using the proposed network. It is seen that when no link is faulty, the ability of compensation is greater than that of the reconstruction strategy using single-track switches but is less than that of the strategy allowing the horizontal or vertical compensation paths to the spares on the boundary of mesh-arrays to cross. Finally considering that the proposed architectures have several routes to connect healthy PEs with each other, avoiding faulty PE, we propose an algorithm for coping with simultaneous faults of PEs and interconnection links
Keywords :
VLSI; circuit optimisation; compensation; integrated circuit yield; multiprocessor interconnection networks; parallel architectures; reconfigurable architectures; wafer-scale integration; compensation algorithm; doubly duplicated links; interconnection networks; link faults; mesh-arrays; processor element; reconfigurable architectures; simultaneous faults; Computer architecture; Computer network reliability; Computer science; Computer simulation; Concurrent computing; Multiprocessor interconnection networks; Reconfigurable architectures; Switches; Very large scale integration; Wiring;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-7107-6
DOI :
10.1109/DFTVS.1995.476943
