Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron

The effect of process variability on power and performance of integrated circuits can only be reduced with statistical optimization techniques. In this paper, we examine optimum V_DD-V_T design for minimizing power in deep-submicron CMOS circuits and introduce highly-efficient algorithm for yield constrained optimum power operation to include the impact of process variability and avoid the limitations of commonly employed deterministic optimization techniques. The yield constraint becomes active as the optimization concludes, eliminating the problem of overdesign in worst-case approach. The experimental results, obtained with ISCAS´85 circuits implemented in UMC 1P8M 65nm technology, demonstrate feasibility of the method.