A novel ternary more, less and equality circuit using recharged semi-floating gate devices

This paper presents a novel ternary more, less and equality (MLE) circuit implemented with recharged semi-floating gate transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadencereg Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm general purpose bulk CMOS process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is plusmn0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates