2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing

This paper describes the design of a fully integrated phase-locked loop for clock and data recovery applications. A two-stage ring oscillator modified for high-speed applications is proposed. The new proposed two-stage VCO features a self-skewing local action per stage. This leads to a significant improvement in speed up to 3 times than the conventional one. An operation up to 2GHz under 0.9mW power consumption with 1V supply is achieved using a standard 0.18 mum process. The chip active area is 0.1times0.1 mm²