Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes

This paper discusses the design of a high-speed encoder for low density parity check (LDPC) codes. To minimize hardware costs and memory requirements of such encoders, a class of high-performance quasi-cyclic LDPC codes which can be encoded in linear time has been proposed by designing the parity check matrix in a triangular plus dual-diagonal form. Based on the proposed codes, parallel architectures and pipelining technology have been used to increase the throughput of encoders. Moreover, collisions which occur when parallel processors contend for write access to the same memory module are avoided by exploiting an iterative encoding approach which involves repeated usage of the processors. The implementation results into field programmable gate array (FPGA) devices indicate that the encoder for the LDPC code with a block length of 2048 and a code rate of 0.5 attains a throughput of 12.8 Gbit/s using 352 exclusive-OR gates