Title :
Structured Placement with Topological Regularity Evaluation
Author :
Nakatake, Shigetoshi
Author_Institution :
Dept. of Inf. & Media Sci., Kitakyushu Univ., Fukuoka
Abstract :
This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is a kind of standard representation of a sequence-pair. We extract regular structures from a single-sequence in 0(n), and then evaluate the structures by quantifying the regularity as an objective function. Besides, we propose a new simulated annealing (SA) framework, called dual SA, where we convey a constructive feature to an SA framework, so that it attains a placement balancing the size of regular structures against the area efficiency. In experiments, we apply our structured placement to analog block designs, and reveal the definite advantage that our placements contain many regular structures such as rows and arrays without increasing the chip area and the wire length, compared to the existing placement.
Keywords :
analogue circuits; circuit layout CAD; integrated circuit layout; simulated annealing; analog block designs; block placement; floorplanning; placement balancing; simulated annealing; structured placement; topological regularity evaluation; Circuit optimization; Degradation; Humans; Signal design; Simulated annealing; Stochastic processes; Stochastic systems; Temperature; Topology; Wire;
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
DOI :
10.1109/ASPDAC.2007.357988