Title :
A 1/4 rate linear phase detector for PLL-based CDR circuits
Author :
Saffari, Mohsen ; Atarodi, Mojtaba ; Tajalli, Armin
Author_Institution :
Sharif Univ. of Technol.
Abstract :
In this paper, a new frac14 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits is suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18mum CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply
Keywords :
CMOS integrated circuits; clocks; network topology; phase detectors; phase locked loops; 0.18 micron; 1.8 V; 16 mA; CMOS technology; PLL-based CDR circuits; clock and data recovery circuits; duty cycle variation; linear PD structure; linear phase detector structure; Circuits; Clocks; Jitter; Latches; Phase detection; Phase frequency detector; Pulse generation; Signal generators; Space vector pulse width modulation; Strontium;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693326
