DocumentCode
2544840
Title
A Novel Performance-Driven Topology Design Algorithm
Author
Pan, Min ; Chu, Chris ; Patra, Priyadarshan
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
244
Lastpage
249
Abstract
This paper presents a very efficient algorithm for performance-driven topology design for interconnects. Given a net, it first generates A-tree topology using table lookup and net-breaking. Then a performance-driven post-processing heuristic not restricting to A-tree topology improves the obtained topology by considering the sink positions, required time and load capacitance to achieve better timing. Experimental results show that our new technique can produce topologies with better timing and is hundreds of times faster than traditional approach.
Keywords
circuit CAD; integrated circuit design; integrated circuit interconnections; table lookup; tree searching; A-tree topology; interconnects design; net-breaking technique; performance-driven topology design algorithm; table lookup; Algorithm design and analysis; Approximation algorithms; Capacitance; Circuit topology; Delay effects; Design engineering; Integrated circuit interconnections; Routing; Table lookup; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.357993
Filename
4196039
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