Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
Abstract :
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interconnect information. Hence, high-quality and fast global routers are in great demand. In this paper, we propose two major techniques to improve the extremely fast global router, FastRoute (Pan and Chu, 2006) in terms of solution quality : (1) monotonic routing, (2) multi-source multi-sink maze routing. The new router is called FastRoute 2.0. Experimental results show that FastRoute 2.0 can generate high-quality routing solutions with fast runtime compared with three state-of-the-art academic global routers FastRoute, Labyrinth (Kastner et al., 2000) and Chi Dispersion router (Hadsell and Madden, 2003). On the set of benchmarks used in Pan and Chu, 2006 and Hadsell and Madden (2003), the total overflow of FastRoute 2.0 is 98, compared to 1012 (FastRoute), 2846 (Labyrinth) and 1271 (Chi Dispersion Router). The runtime of FastRoute 2.0 is 73% slower than FastRoute, but 78times and 37times faster than Labyrinth and Chi Dispersion router. The promising results make it possible to integrate global routing into early design stages. This could dramatically improve the design solution quality.
Keywords :
circuit CAD; integrated circuit design; integrated circuit interconnections; FastRoute 2.0; advanced IC technology; design solution quality; extremely fast global router; high-quality routing solutions; monotonic routing; multisource multisink maze routing; Clocks; Delay estimation; Integrated circuit interconnections; Routing; Runtime; Timing; Topology; Very large scale integration; White spaces; Wire;