DocumentCode :
2544931
Title :
Future devices for information processing
Author :
Cavin, R. ; Zhirnov, Victor V.
Author_Institution :
Semicond. Res. Corp., Research Triangle Park, NC, USA
fYear :
2005
fDate :
12-16 Sept. 2005
Firstpage :
7
Lastpage :
12
Abstract :
Current CMOS devices operate at about six orders of magnitude above the kBTln2 Joules/bit switching limit imposed by physics. Nevertheless, it can be shown that continued scaling of device features that are then densely packed and operated at attainable frequencies will result in the generation of thermal loads that cannot be managed by any known heat removal technology. We discuss possible successor/complementary logic devices that reduce the level of heat generation and we discuss new nonvolatile memory techniques that could radically impact information processing architectures and hence the performance requirements for logic devices.
Keywords :
CMOS integrated circuits; CMOS logic circuits; CMOS memory circuits; thermal management (packaging); CMOS devices; complementary logic devices; heat generation; heat removal technology; information processing architecture; nonvolatile memory techniques; successor logic devices; thermal load; CMOS technology; Electrons; Energy barrier; Equations; Information processing; Logic devices; Physics; Thermal management; Tunneling; Uncertainty;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
Type :
conf
DOI :
10.1109/ESSCIR.2005.1541550
Filename :
1541550
Link To Document :
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